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早稲田大学ＩＴ研究機構＞プロジェクト＞アドバンストチップマルチプロセッサ研究所《概要》＞活動報告（論文）

プロジェクト研究所 《活動報告》

アドバンストチップマルチプロセッサ研究所

≪２００８年度≫

・論文

  1. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, "Multiple-paths Search with Concurrent Thread Scheduling for Fast AND/OR Tree Search", Proc. of International Conference on Complex, Intelligent and Software Intensive Systems (CISIS 2009), Mar. 2009


  2. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, "Parallel and Concurrent Search for Fast AND/OR Tree Search on Multicore Processors", Proc. of the IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2009), Feb. 2009


  3. Hiroki Mikami, Jun Shirako, Masayoshi Mase, Takamichi Miyamoto, Hirofumi Nakano, Fumiyo Takano, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors", Proc. of 14th Workshop on Compilers for Parallel Computing(CPC 2009), Jan. 2009


  4. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API", Proc. of IEEE International Symposium on Advances in Parallel and Distributed Computing Techniques (APDCT-08), Dec. 2008


  5. 宮本孝道, 浅香沙織, 見神広紀, 間瀬正啓, 木村啓二, 笠原博徳, "情報家電用マルチコア並列化APIを生成する自動並列化コンパイラによる並列化の評価", 情報処理学会論文誌　コンピューティングシステム, Vol. 1, No. 3, pp.83-95, Dec. 2008


  6. Jun Shirako, Keiji Kimura, Hironori Kasahara, "Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler", Proc. of International SoC Design Conference　(ISOCC 2008), Nov. 2008


  7. Jun Shirako, Hironori Kasahara, Vivek Sarkar, "Language Extensions in Support of Compiler Parallelization", Lecture Notes in Computer Science, Springer, Vol. 5234, pp.78-94, Oct. 2008


  8. 和田 康孝, 林 明宏, 益浦 健, 白子 準, 中野 啓史, 鹿野 裕明, 木村啓二, 笠原博徳, "ヘテロジニアスマルチコア上でのスタティックスケジューリングを用いたMP3エンコーダの並列化", 情報処理学会論文誌コンピューティングシステム, Vol. 1, No. 1, pp.105-119, Jun. 2008


  9. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture", Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008), Jun. 2008


  10. Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function", Proc. of IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008, Apr. 2008


  11. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multi-core Architecture that Enables 54x AAC-LC Stereo Encoding", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp.902-910, Apr. 2008


  12. Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor", 電子情報通信学会論文誌"Special Section on Advanced Technologies in Digital LSIs and Memories", Vol. E91-C, No. 4, pp.432-439, Apr. 2008