早稲田大学IT機構  
                 home


プロジェクト研究所 《活動報告》

システムLSI研究所

≪2008年度≫

成果発表

・論文発表20件<国内(和文)3件、国際(欧文)17件)

【国内】
  1. 山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫, "SIMD型プロセッサコアの面積/遅延見積もり", 情報処理学会論文誌, ,no.10, pp.3462-3481, 2008年10月.


  2. 平塚 誠一郎, 後藤 敏, 池永 剛, "適応的な画素間引きと計算予測打ち切りによる超低計算量動き検出アルゴリズム", 電子情報通信学会論文誌D, Vol. J91-D, No. 8, pp.2080-2088, Aug 2008.


  3. 平塚 誠一郎、後藤 敏、池永 剛, "モバイル向け0.3mW 1.4mm2 動き検出プロセッサLSI", 電子情報通信学会論文誌C, Vol. J91-C, No. 5, pp.304-310, May 2008.


【国際】
  1. S. Chen, Z. Xu, and T. Yoshimura, "A generalized v-shaped multi-level method for large scale Foorplanning", Proc. 10th International Symposium on Quality Electronic Design, San Jose, USA, March 2009


  2. M.-F. Chiang, T. Okamoto, and T. Yoshimura, "Lagrangian relaxation based register placement for high-performance circuits”, Proc. 10th International Symposium on Quality Electronic Design, San Jose, USA, March 2009


  3. Liangwei Ge, Song Chen and Takeshi Yoshimura, "Exploration of Schedule Space by Random Walk", IPSJ Transactions on System LSI Design Methodology, Vol.2, Feb 2009


  4. Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga,"HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis", IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, pp 594-608, Feb. 2009.


  5. Wen JI, Yuta ABE, Takeshi IKENAGA, Satoshi GOTO, "A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule", IEICE Special Section on VLSI Design and CAD Algorithms, Vol.E91-A, No.12 pp.3622-3629, Dec. 2008.


  6. Y. Yang and S. Kimura, “Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration," IEICE Trans. Fundamentals, vol.E91-A, No.12, pp.3431-3442, Dec. 2008.


  7. L. Chen, T. Horiyama, Y. Nakamura and S. Kimura, "Fine-Grained Power Gating Based on the Controlling Value of Logic Elements," IEICE Trans. Fundamentals, vol.E91-A, No.12, pp.3531-3538, Dec. 2008.


  8. Yiqing Huang, Qin Liu and Takeshi Ikenaga, "Macroblock Feature based Complexity Reduction for H.264/AVC Motion Estimation", IEICE Trans. Fundamentals, Vol. E91-A, No. 10, pp. 2934-2944, Oct. 2008.


  9. Qin Liu, Yiqing Huang, Satoshi Goto, Takeshi Ikenaga, "Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm", IEICE Trans. Fundamentals, Vol. E91-A, No. 8, pp. 1935-1943, Aug. 2008.


  10. Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga, "Content-Aware Fast Motion Estimation for H.264/AVC", IEICE Trans. Fundamentals, Vol. E91-A, No. 8, pp. 1944-1952, Aug. 2008.


  11. Liangwei Ge, Song Chen, Y.Nakamura and T.Yoshimura, "A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition", IPSJ Trans. On SLDM, Vol.1, No.1, pp67-77, 2008.8


  12. Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, "Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures," IPSJ Tras. on SLDM, Vol.1, pp.78-90, Aug.2008.


  13. Zhenyu Liu, Lingfeng Li, Yang Song, Shen Li, Satoshi Goto, Takeshi Ikenaga, "Motion Feature and Hadamard Coefficient based Fast Multiple Reference Frame Motion Estimation for H.264", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 18, No. 5, pp.620-632, May 2008.


  14. Song Chen and T.Yoshimura, "Fixed-Outline Floorplanning: Block Position Enumeration and a New Method for Calculating Area Costs", IEEE Transactions on CAD Vol.27, No.5, pp858-871, 2008.5((高位レベルでの配置の正確な評価を行うためのフロアプラン問題に関して,高精度の解を高速に計算することができるIARFP と呼ばれる新しい手法を開発した。標準ベンチマークデータによる評価では,既存の代表的な手法を,計算時間と解の良さの点で大きく凌駕することが確認された。)


  15. Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, "Low Power LDPC Decoder Architecture Based on Intermediate Message Compression Technique", IEICE Trans. on Fundamental, vol.E92-A, No.4, Apr., 2008.


  16. Yiqing Huang, Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga, "Inter Search Mode Reduction Based Parallel Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC", IEICE Trans. Fundamentals, Vol. E91-A, No. 4, pp. 987-997, Apr. 2008.


  17. Qin Liu, Seiichiro Hiratsuka, Kazunori Shimizu, Shinsuke Ushiki, Satoshi Goto, Takeshi Ikenaga, "A 41mW VGA@30fps Quadtree Video Encoder for Video Surveillance Systems", IEICE Trans. Electronics, Vol. E91-C, No. 4, pp. 449-456, Apr. 2008.